Embodiments relate to image sensors in general and, in particular, to novel architectures for single-slope column-parallel analog-to-digital converters (ADCs).
Proliferation of complementary metal-oxide-semiconductor (CMOS) image sensors (CIS) in consumer markets has been accelerated by the adoption of CIS in many popular consumer electronics applications, including mobile handsets. This trend, together with the rapid growth in smartphone markets, has led manufacturers and consumers to desire apparently ever-increasing resolutions in their CIS applications. In this context, CIS designers have remained constrained by issues relating to die sizes and aspect ratios, costs, power consumption, and others.
As sensor resolution increases, operation of the sensors in desired frame rates (e.g., full HD frame rate) involves higher data conversion rates. Many typical applications of high resolution sensors employ single-slope column-parallel analog-to-digital converters (ADCs) at least to achieve these higher data conversion rates while dissipating low power. For example, in comparison to competing architectures, like global serial pipeline ADC architectures, the column-parallel ADC architecture can achieve lower read noise, and thus higher dynamic range, due to reduced bandwidth readout circuit for each column's ADC.
Typical CIS Applications tend to experience both row-wise and column-wise noise from various sources. For example, some row-wise noise may result from power supply movement, and some column-wise noise, for example, including column fixed-pattern noise (CFPN), may result from variations in column circuits. The various types of noise can cause undesirable effects, including limitations on the sensitivity of the CIS, visible artifacts in the CIS output, etc. Thus, it may be desirable to provide techniques for addressing these row-wise and/or column-wise noise sources.